There is known an inter-device interface method between a first device operating at timings of a first clock and a second device operating at timings of a second clock which is a cycle of 1/n times the first clock (see, for example, Patent Document 1). A first switching means in the first device converts parallel data with a predetermined bit length which are transmitted from the first device to the second device into serial data by every m-bit unit where m≦n. A serial data interface line for every m-bit unit transmits the serial data converted by the first switching means to the second device. A second switching means in the second device receives at a timing of the second clock the serial data transmitted by the serial data interface line and converts the data into parallel data with a predetermined bit length. A data conversion control means in the second device executes a data switching instruction for the first switching means and a data switching instruction for the second switching means at a timing of the second clock. A data switching instruction line transmits the data switching instruction for the first switching means by the data conversion control means to the first device. In one cycle of the first clock, parallel data with a predetermined bit length are divided into serial data in m-bit units, and are transmitted from the first device to the second device at a timing of the second clock.
Further, there is known a memory device which has a plurality of redundancy memories each having pluralities of ordinary memory cell blocks and spare memory cell blocks and a plurality of flip flops each connected in series, each storing a numeric value, and respectively outputting numeric values to the plurality of redundancy memories (see, for example, Patent Document 2). A non-volatile memory stores a seed value. A pseudo-random number generating circuit generates reproducible pseudo-random numbers based on the seed value stored in the non-volatile memory, and serially outputs pseudo-random numbers to the plurality of flip flops. The plurality of flip flops serially transfer, in synchronization with a clock signal, the pseudo-random numbers outputted by the pseudo-random number generating circuit. Each of the plurality of redundancy memories switch one of the plurality of ordinary memory cell blocks to a spare memory cell block according to numeric values stored in the plurality of flip flops.
Further, there is known a serial interface circuit which has a shift register generating an address signal and a second data signal based on a first data signal and a clock signal, and a register generating unit writing the second data signal in a register specified by an address decoder (see, for example, Patent Document 3). An address control circuit outputs a first address value specifying a register to the address decoder based on the address signal. A control circuit outputs to the address control circuit a control signal allowing outputting the first address value and writing the second data signal in the register or not allowing outputting the first address value based on the clock signal and a standby signal.
[Patent Document 1] Japanese Laid-open Patent Publication No. 5-250316
[Patent Document 2] Japanese Laid-open Patent Publication No. 2013-122800
[Patent Document 3] Japanese Laid-open Patent Publication No. 2005-266856
In every type of semiconductor chip, the number of shift registers and/or the shift register length is different. Therefore, the data transmission unit transmitting data to the shift registers have a different configuration in every type of semiconductor chip and is difficult to be commonized.